# File lib/rouge/lexers/verilog.rb, line 38
      def self.keywords_type
        @keywords_type ||= Set.new %w(
          and bit buf bufif0 bufif1 byte cell chandle class cmos const disable
          edge enum event highz0 highz1 initial inout input int integer join
          logic longint macromodule medium nand negedge nmos nor not
          notif0 notif1 or output packed parameter pmos posedge pull0 pull1
          pulldown pullup rcmos real realtime ref reg repeat rnmos rpmos rtran
          rtranif0 rtranif1 scalared shortint shortreal signed  specparam
          static string strength strong0 strong1 struct supply0 supply1 tagged
          time tran tranif0 tranif1 tri tri0 tri1 triand trior trireg union
          unsigned uwire var vectored virtual void wait wand weak[01] wire wor
          xnor xor
        )
      end